1. Field of the Invention
The present invention relates to a discharge circuit, and to a power supply device incorporating a discharge circuit.
2. Description of Related Art
Conventionally, a power supply device that is supplied with an AC (alternating-current) input voltage has, as a means for reducing differential mode noise (also called normal mode noise), an X capacitor CX connected between a line terminal L and a neutral terminal N (see FIG. 9A).
With a power supply device having an X capacitor CX (and an electronic device incorporating it), to protect a user from a serious electric shock hazard who may touch the electric plug just after it is disconnected from a wall receptacle, it is an obligation to meet a discharge standard of the X capacitor CX (IEC 60950-1, IEC 60065, or Japan's Electrical Appliances and Materials Safety Act (Attached Table 8)).
FIGS. 9A and 9B are circuit diagrams of conventional examples of discharge circuits for discharging residual electric charge in an X capacitor CX on an input shut-off The discharge circuit shown in FIG. 9A includes a discharge resistor Rdchg which is connected in parallel with the X capacitor CX. On the other hand, the discharge circuit shown in FIG. 9B includes a semiconductor device 200 which controls the discharging of the X capacitor CX by monitoring a divided voltage Vd of the AC input voltage.
An example of the above-mentioned conventional technology is seen in JP-A-2014-017990.
In the discharge circuit shown in FIG. 9A, the discharge resistor Rdchg constantly consumes electric power unnecessarily, and this has been hampering power saving (in particular, stand-by power reduction) in power supply devices.
On the other hand, in the discharge circuit shown in FIG. 9B, input voltage dividing resistors Ra and Rb and a noise elimination capacitor Ca constitute an RC time constant circuit, and this results in a dull response of the divided voltage Vd on an input shut-off. Thus, with the semiconductor device 200, which detects an input shut-off by monitoring the DC level of the divided voltage Vd, a delay may arise in the timing of the detection of an input shut-off (and hence in the timing of the start of the discharging of the X capacitor CX), leading in the worst case to a failure to meet the discharge standard mentioned above.